1. Field of the Invention
The present invention generally relates to a system bus control system for a multiprocessor system including a plurality of processors.
2. Description of the Prior Art
A multiprocessor system includes a plurality of processors capable of performing respective processes in order to improve the performance of the overall system. Such a multiprocessor system needs a lock control among the processors in order to avoid collisions of access to one or a plurality of resources. Such a lock control can be realized by providing a lock control area in a shared memory (resource) which can be accessed by all the processors, and the right to use the resource is assigned on the basis of the contents of the lock control area. The above lock control using the lock control area absolutely requires that all the processors attempt to acquire the right to exclusively use the shared resource in the same procedures and the processors other than one processor having the exclusive right to use the shared resource do not interrupt execution of the process by the above processor.
More particularly, in the procedure for acquiring the right to exclusively use the resource, a processor reads an access condition for exclusive use. Information (for example, a flag) concerning such an access condition is stored in a register or a storage area connected to the system bus. For example, if the flag indicating the access condition is "0", no processors are using the shared resource. If the flag is "1", one of the processors is exclusively using the shared resource. A processor which requests to use the shared resource confirms that the flag is "0", and accesses the shared resource to write data therein. If an ordinary write access is applied to the flag area, the lock control cannot be established. Further, there is a possibility that two or more processors may simultaneously acquire the right to use the shared resource during the above sequence of reading the access condition, checking it and writing data into the shared resource. For example, when a processor checks the access condition, another processor has checked the access condition and has just started the write operation.
In order to eliminate the problem resulting from the hardware, a processor having a command specifically used for lock control is required. Such a processor asserts a signal indicating the lock control while the processor is executing a lock control command, and successively performs the condition read, check and write operations (in other words, the processor does not release the system bus or accept an interrupt request during the interval between the read and write operations) in order to prevent the other processors from generating interrupt requests.
More particularly, an arbiter performing an arbitration of accesses to the system bus supervises a lock control signal (LOC) indicative of the locking period and generated by a processor. While the lock control signal is being asserted, the arbiter does not accept command send requests from the other modules (processors) at all. While the lock control signal is being asserted, the other modules cannot issue commands at all, and thus the throughput of the overall system is low. That is, the arbiter allows only the module outputting the lock control signal to use the system bus and prevents the other modules from using the system bus.
However, in practice, the module which has acquired the exclusive use of the system bus uses the system bus intermittently, and the total of intervals during which the module does not use the system bus is great. Even when the module does not use the system bus, the other modules cannot use the system bus. Hence, the system bus is not efficiently used and the throughput of the overall system is low.